TEAC PD-H500C Service Manual

Cover page of TEAC PD-H500C Service Manual

Service Manual for TEAC PD-H500C, downloadable as a PDF file.

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Compact Disc Player
PD-H500C
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Compact Disc Player
PD-H500C
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SERVICE MANUAL
3
TC9432AF/ TC9462AF (Digital Signal Processor)
PIN No. NAME
I/O
FUNCTIONAL DESCRIPTION
REMARKS
TEST0
HSO
UHSO
EMPH
LRCK
VSS
BCK
AOUT
DOUT
MBOV
IPF
SBOK
CLCK
VDD
VSS
DATA
SFSY
SBSY
SPCK
SPDA
COFS
MONIT
VDD
TESIO0
P2VREF
HSSW
ZDET
PDO
TMAXS
TMAX
With pull-up resistor.
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-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2-state output (PVREF,HiZ)
-
3-state output
(P2VREF,PVREF,VSS)
-
3-state output
(P2VREF,HiZ,VSS)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Test mode terminal. Normally, keep at open.
Playback speed mode flag output terminal.
Subcode Q data emphasis flag output terminal.
Emphasis ON at "H" level and OFF at "L" level.
The output polarity can invert by command.
Channel clock output terminal. (44.1 kHz)
L-ch at "L" level and R-ch at "H" level.
The output polarity can invert by command.
Digital GND terminal.
Bit clock output terminal. (1.4112 MHz)
Audio data output terminal.
Digital data output terminal.
Buffer memory over signal output terminal.
Over at "H" level.
Correction flag output terminal.
At "H " level, AOUT output is made to correction
impossibility by C2 correction processing.
Subcode Q data CRCC check adjusting result output
terminal. The adjusting result is OK at "H" level.
Subcode P~W data readout clock input/output termi-
nal. This terminal can select by command bit.
Digital power supply voltage terminal.
Digital GND terminal.
Subcode P~W data output terminal.
Playback frame sync signal output terminal.
Subcode block sync signal output terminal.
Processor status signal readout clock output terminal.
Processor status signal output terminal.
Correction frame clock output terminal. (7.35 kHz)
Internal signal (DSP internal flag and PLL clock) output
terminal. Selected by command.
Digital power supply voltage terminal.
Test input/output terminal. Normally, keep at "L" level.
PLL double reference voltage supply terminal.
2/4 times speed at "VREF" voltage.
1 bit DA converter zero detect flag output terminal.
Phase difference signal output terminal of EFM signal
and PLCK signal.
TMAX detection result output terminal. Selected by
command bit (TMPS).
TMAX detection result output terminal. Selected by
command bit (TMPS).
-
O
O
O
O
-
O
O
O
O
O
O
I/O
-
-
O
O
O
O
O
O
O
-
I
-
O
O
O
O
O
UHSO
HSO
PLAYBACK SPEED
H
H
Normal
H
L
2 times
L
H
4 times
L
L
-
DIFFERENCE RESULT
TMAX OUTPUT
Longer than fixed ferq.
"P2VREF"
Shorter than fixed freq.
"VSS"
Within the fixed freq.
"HiZ"
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SERVICE MANUAL
5
PIN No. NAME
I/O
FUNCTIONAL DESCRIPTION
REMARKS
DMOUT
CKSE
DACT
TESIN
TESIO1
VSS
PXI
PXO
VDD
XVSS
XI
XO
XVDD
DVSR
RO
DVDD
DVR
LO
DVSL
TEST1
TEST2
TEST3
BUS0
BUS1
BUS2
BUS3
VDD
VSS
BUCK
CCE
TEST4
TSMOD
RST
With pull-up resistor.
With pull-up resistor.
With pull-up resistor.
Analog input.
Analog input.
-
-
-
-
-
-
-
-
-
-
-
-
-
With pull-up resistor.
With pull-up resistor.
With pull-up resistor.
Schmit input.
With pull-up resistor.
-
-
Schmit input.
Schmit input.
With pull-up resistor.
With pull-up resistor.
With pull-up resistor.
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
This terminal controls IO0~IO3 terminal.
At "L" level time, IO0, 1 out feed equalizer signal of
2-state PWM. IO2, 3 out disk equalizer signal of 2-state
PWM.
Normally, keep at open.
DAC test mode terminal. Normally, keep at open.
Test input terminal. Normally, keep at "L" level.
Test input/output terminal. Normally, keep at "L" level.
Digital GND terminal.
Crystal oscillator connecting input terminal for DSP.
Normally, keep at "L" level.
Crystal oscillator connecting output terminal for DSP.
Digital power supply voltage terminal.
Oscillator GND terminal for system clock.
Crystal oscillator connecting input terminal for system
clock.
Crystal oscillator connecting output terminal for sys-
tem clock.
Oscillator power supply voltage terminal for system
clock.
Analog GND terminal for DA converter. (R-ch)
R channel data forward output terminal.
Analog supply voltage terminal for DA converter.
Reference voltage terminal for DA converter.
L channel data forward output terminal.
Analog GND terminal for DA converter. (L-ch)
Test mode terminal. Normal, keep at open.
Test mode terminal. Normal, keep at open.
Test mode terminal. Normal, keep at open.
Micom interface data input/output terminal.
Digital Ppower supply voltage terminal.
Digital GND terminal.
Micom interface clock input terminal.
Command and data sending/receiving chip enable sig-
nal input terminal.
The bus
line becomes active at "L" level.
Test mode terminal. Normal, keep at open.
Local test mode selection terminal.
Reset signal input terminal. Reset at "L" level.
I
I
I
I
I
-
I
O
-
-
I
O
-
-
O
-
-
O
-
I
I
I
I/O
I/O
I/O
I/O
-
-
I
I
I
I
I

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